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3-65 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 tc835 features n upgrade of pin-compatible tc7135, icl7135, max7135 and si7135 n guaranteed 200 khz operation n single 5v operation with tc7660 n multiplexed bcd data output n uart and microprocessor interface n control outputs for auto-ranging n input sensitivity ............................................ 100 m v n no sample and hold required applications n personal computer data acquisition n scales, panel meters, process controls n hp-il bus instrumentation ordering information temperature part no. package range tc835cbu 64-pin pqfp 0 c to +70 c tc835ckw 44-pin pqfp 0 c to +70 c TC835CPI 28-pin plastic dip 0 c to +70 c note: tape and reel available for 44-pin pqfp packages. personal computer data acquisition a/d converter general description the tc835 is a low-power, 4-1/2 digit (0.005% resolu- tion), bcd analog-to-digital converter (adc) that has been characterized for 200 khz clock rate operation. the five conversions per second rate is nearly twice as fast as the icl7135 or tc7135. the tc835 (like the tc7135) does not use the external diode-resistor roll-over error compen- sation circuits required by the icl7135. the multiplexed bcd data output is perfect for interfac- ing to personal computers. the low-cost, greater than 14- bit high-resolution, and 100 m v sensitivity makes the tc835 exceptionally cost-effective. microprocessor-based data acquisition systems are supported by the busy and strobe outputs, along with the run/hold input of the tc835. the overrange, under- range, busy, and run/hold control functions and multiplexed bcd data outputs make the tc835 the ideal converter for m p-based scales and measurement systems and intelligent panel meters.* the tc835 interfaces with full-function lcd and led display decoder/drivers. the underrange and overrange outputs may be used to implement an auto- ranging scheme or special display functions. *see application notes 16 and 17 for microprocessor interface tech- niques. data bus control address bus 6522 -via- pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 ca1 ca2 pb5 pb4 pb0 pb3 pb2 pb1 channel selection gain selection 1y 2y 3y 1b 2b 3b sel 1a 2a 3a 157 pol or ur d5 b8 b4 b2 b1 d1 d2 d3 d4 stb r/h v + ref cap buf az int input + v r input analog common dgnd 5v ref voltage 10 14 16 15 8 11 3 9 gain: 10, 20, 50, 100 15v 15v channel 1 channel 2 channel 3 channel 4 differential multiplexer dg529 d a d b wr a 1 a 0 en 5v + + f in f in + lh0084 tc835 typical application tc835-8 11/5/96
3-66 telcom semiconductor, inc. personal computer data acquisition a/d converter tc835 absolute maximum ratings* (note 1) positive supply voltage ............................................. +6v negative supply voltage ............................................ - 9v analog input voltage (pin 9 or 10) ........ v + to v C (note 2) reference input voltage (pin 2) .......................... v + to v C clock input voltage ............................................. 0v to v + operating temperature range .................... 0 c to +70 c storage temperature range ................ C 65 c to +150 c lead temperature (soldering, 10 sec) ................. +300 c notes: 1. functional operation is not implied. 2. limit input current to under 100 m a if input voltages exceed supply voltage. 3. full-scale voltage = 2v. 4. v in = 0v. 5. 0 c t a +70 c. 6. external reference temperature coefficient less than 0.01 ppm/ c. 7. C 2v v in +2v. error of reading from best fit straight line. 8. |v in | = 1.9959. 9. test circuit shown in figure 1. 10. specification related to clock frequency range over which the tc835 correctly performs its various functions. increased errors result at higher operating frequencies. electrical characteristics: t a = +25 c, f clock = 200 khz, v + = +5v, v C = C 5v, unless otherwise specified. symbol parameter test conditions min typ max unit analog display reading with notes 3 and 4 C0.0000 0.0000 +0.0000 display zero volt input reading tc z zero reading v in = 0v 0.5 2 m v/ c temperature coefficient note 5 tc fs full-scale v in = 2v 5 ppm/ c temperature coefficient notes 5 and 6 nl nonlinearity error note 7 0.5 1 count dnl differential linearity error note 7 0.01 lsb display reading in v in = v ref +0.9996 +0.9998 +1.0000 display ratiometric operation note 3 reading fse full-scale symmetry Cv in = +v in 0.5 1 count error (roll-over error) note 8 i in input leakage current note 4 1 10 pa e n noise peak-to-peak value not exceeded 95% of time 15 m v p-p digital i il input low current v in = 0v 10 100 m a i ih input high current v in = +5v 0.08 10 m a v ol output low voltage i ol = 1.6 ma 0.2 0.4 v v oh output high voltage b 1 , b 2 , b 4 , b 8 , d 1 Cd 5 i oh = 1 ma 2.4 4.4 5 v busy, polarity, overrange, i oh = 10 m a 4.9 4.99 5 v underrange, strobe f clk clock frequency note 10 0 200 1200 khz power supply v + positive supply voltage 4 5 6 v v C negative supply voltage C 3 C 5 C 8 v i + positive supply current f clk = 0 hz 1 3 ma i C negative supply current f clk = 0 hz 0.7 3 ma pd power dissipation f clk = 0 hz 8.5 30 mw package power dissipation (t a 70 c) 28-pin plastic dip ............................................. 1.14w 44-pin pqfp .................................................... 1.00w 64-pin pfp .......................................................1.14w *static-sensitive device. unused devices must be stored in conductive material. protect devices from static discharge and static fields. stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
3-67 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 personal computer data acquisition a/d converter tc835 pin configurations 27 28 29 30 31 32 33 7 4 3 2 1 tc835ckw 12 13 14 15 17 18 44 43 42 41 39 38 40 16 37 36 35 34 19 20 21 22 26 8 25 9 24 10 23 11 5 6 nc nc nc analog com ref in v ur or strobe nc nc nc nc run/hold dgnd polarity d2 nc nc clk in nc int out az in buff out ref cap ?nput +input v+ nc nc ref cap+ nc nc (msd) d5 (lsb) b1 b2 b4 (msb) b8 d4 d3 nc nc d1 (lsd) busy notes: TC835CPI 1 2 3 4 run/hold 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 strobe overrange b4 d3 d2 d1 (lsd) busy clock in polarity digtal gnd underrange b2 (lsb) b1 (msd) d5 v + + input ? input c ref c ref buff out az in int out analog com ref in v d4 b8 (msd) + 1. nc = no internal connection. 2. pins 9, 25, 40 and 56 are connected to the die substrate. the potential at these pins is approximately v + . no external connections should be made. 63 4 3 2 1 16 15 14 10 9 8 7 6 5 12 11 40 41 42 43 44 45 46 34 35 36 37 38 39 48 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 61 60 59 58 57 56 55 54 53 52 51 50 49 64 tc835cbu int out nc az in v+ nc +input nc buff out buf cap nc sub buf cap+ nc ?nput nc nc nc nc nc nc d1 strobe run/hold dgnd pol sub clk in busy d2 32 nc 62 nc 13 47 nc notes 1 & 2 nc nc nc nc nc nc nc nc overrange underrange sub v ref in analog com nc nc d3 nc nc nc nc d4 b3 b4 b2 sub b1 d5 nc nc nc nc
3-68 telcom semiconductor, inc. + + + + in in ref analog com in sw i sw r sw z sw i sw 1 sw z sw iz sw z integrator switch closed switch open sw ri + sw ri comparator to digital section sw ri + sw ri analog input buffer r int c int c ref c sz + + + + in in ref analog com in sw i sw r sw z sw i sw 1 sw z sw iz sw z integrator switch closed switch open sw ri + sw ri comparator to digital section sw ri + sw ri analog input buffer r int c int c ref c sz + + + + in in ref analog com in sw i sw r sw z sw i sw 1 sw z sw iz sw z integrator analog input buffer sw ri + sw ri comparator to digital section sw ri + sw ri r int c int c ref c sz figure 3a. analog circuit function diagram figure 1. test circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 100 k w analog gnd 100 k w signal input 0.1 ? set v ref = 1v v ref in analog common int out az in buff out c ref c ref input + input d5 (msd) b1 (lsb) b2 v + underrange overrange strobe run/hold digtal gnd polarity clock in busy (lsd) d1 d2 d4 (msb) b8 b4 d3 + 5v 1 ? 100 k w 1 ? 0.47 ? v ref in clock input 120 khz ?v + tc835 buffer logic input v + figure 3d. reference voltage integration cycle + + + + in in ref analog com in sw i sw r sw z sw i sw 1 sw z sw iz sw z integrator switch closed switch open sw ri + sw ri comparator to digital section sw ri + sw ri analog input buffer r int c int c ref c sz figure 2. digital logic input figure 3c. input signal integration phase figure 3b. system zero phase personal computer data acquisition a/d converter tc835
3-69 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 + + + + in in ref analog com in sw i sw r sw z sw i sw 1 sw z sw iz sw z integrator switch closed switch open sw ri + sw ri comparator to digital section sw ri + sw ri analog input buffer r int c int c ref c sz figure 3e. integrator output zero phase general theory of operation (all pin designations refer to 28-pin dip) dual-slope conversion principles the tc835 is a dual-slope, integrating analog-to-digital converter. an understanding of the dual-slope conversion technique will aid in following the detailed tc835 opera- tional theory. the conventional dual-slope converter measurement cycle has two distinct phases: (1) input signal integration (2) reference voltage integration (deintegration) the input signal being converted is integrated for a fixed time period. time is measured by counting clock pulses. an opposite polarity constant reference voltage is then inte- grated until the integrator output voltage returns to zero. the reference integration time is directly proportional to the input signal. in a simple dual-slope converter, a complete conversion requires the integrator output to "ramp-up" and "ramp- down." a simple mathematical equation relates the input signal, reference voltage, and integration time: the dual-slope converter accuracy is unrelated to the integrating resistor and capacitor values, as long as they are stable during a measurement cycle. an inherent benefit is noise immunity. noise spikes are integrated, or averaged, to zero during the integration periods. integrating adcs are immune to the large conversion errors that plague succes- sive approximation converters in high-noise environments. (see figure 4.) tc835 operational theory the tc835 incorporates a system zero phase and integrator output voltage zero phase to the normal two- phase dual-slope measurement cycle. reduced system errors, fewer calibration steps, and a shorter overrange recovery time result. the tc835 measurement cycle contains four phases: (1) system zero (2) analog input signal integration (3) reference voltage integration (4) integrator output zero internal analog gate status for each phase is shown in table 1. + ref voltage analog input signal + display switch driver control logic integrator output clock counter polarity control phase control v in v in v full scale 1/2 v full scale variable reference integrate time fixed signal integrate time integrator comparator ' ' figure 4. basic dual-slope converter where: v r = reference voltage t si = signal integration time (fixed) t ri = reference voltage integration time (variable). t si v in (t) dt = 0 1 v r t ri , rc rc for a constant v in : v in = v r . ] [ t ri t si tc835 personal computer data acquisition a/d converter
3-70 telcom semiconductor, inc. personal computer data acquisition a/d converter tc835 system zero (figure 3b) during this phase, errors due to buffer, integrator, and comparator offset voltages are compensated for by charg- ing c az (auto-zero capacitor) with a compensating error voltage. with a zero input voltage the integrator output will remain at zero. the external input signal is disconnected from the internal circuitry by opening the two sw i switches. the internal input points connect to analog common. the reference capacitor charges to the reference voltage poten- tial through sw r . a feedback loop, closed around the integrator and comparator, charges the c az capacitor with a voltage to compensate for buffer amplifier, integrator, and comparator offset voltages. analog input signal integration (figure 3c) the tc835 integrates the differential voltage between the +input and Cinput pins. the differential voltage must be within the device common-mode range; - 1v from either supply rail, typically. the input signal polarity is determined at the end of this phase. reference voltage integration (figure 3d) the previously-charged reference capacitor is con- nected with the proper polarity to ramp the integrator output back to zero. the digital reading displayed is: reading = 10,000 . table 1. internal analog gate status conversion reference cycle phase sw i sw ri sw ri sw z sw r sw 1 sw iz schematic system zero closed closed closed 3b input signal closed 3c integration reference voltage closed* closed 3d integration integrator closed closed 3e output zero *note: assumes a positive polarity input signal. sw ri would be closed for a negative input signal. internal analog gate status C + C integrator output zero (figure 3e) this phase guarantees the integrator output is at 0v when the system zero phase is entered and that the true system offset voltages are compensated for. this phase normally lasts 100 to 200 clock cycles. if an overrange condition exists, the phase is extended to 6200 clock cycles. analog section functional description (in reference to the 28-pin plastic package) differential inputs (+input, pin 10 and Cinput, pin 9) the tc835 operates with differential voltages within the input amplifier common-mode range. the input amplifier common-mode range extends from 0.5v below the positive supply to 1v above the negative supply. within this com- mon-mode voltage range, an 86 db common-mode rejec- tion ratio is typical. the integrator output also follows the common-mode voltage. the integrator output must not be allowed to satu- rate. a worst-case condition exists, for example, when a large positive common-mode voltage with a near full-scale negative differential input voltage is applied. the negative input signal drives the integrator positive when most of its swing has been used up by the positive common-mode voltage. for these critical applications the integrator swing can be reduced to less than the recommended 4v full-scale swing, with some loss of accuracy. the integrator output can swing within 0.3v of either supply without loss of linearity. analog common input (pin 3) analog common is used as the Cinput return during auto-zero and deintegrate. if Cinput is different from analog common, a common-mode voltage exists in the system. this signal is rejected by the excellent cmrr of the converter. in most applications, Cinput will be set at a fixed, known voltage (power supply common, for instance). in this application, analog common should be tied to the same point, thus removing the common-mode voltage from the converter. the reference voltage is referenced to analog common. reference voltage input (ref in, pin 2) the ref in input must be a positive voltage with respect to analog common. two reference voltage circuits are shown in figure 5. ] [ differential input v ref
3-71 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 20 k 6.8 k w w v + 1.25v ref tc04 v + ref in 6.8v zener v + i z v v + analog ground analog common ref in analog common tc835 tc835 latch latch latch latch latch counters control logic multiplexer polarity d5 d4 d3 d2 d1 13 b1 14 b2 15 b4 16 b8 polarity ff msb digit drive signal lsb data output 24 22 25 27 28 26 21 digital gnd clock in run/ hold over range strobe busy under range zero cross detect from analog section integrator output overrange when applicable underrange when applicable system zero 10,001 counts signal inte 10,000 counts (fixed) reference integrate 20,001 counts (max) full measurement cycle 40,002 counts busy expanded scale below d5 d4 d3 d2 d1 100 counts digit scan strobe auto zero signal integrate reference integrate d5 d4 d3 d2 d1 digit scan for overrange first d5 of system zero and reference integrate one count longer. * * * figure 5. using an external reference figure 7. timing diagrams for outputs figure 6. digital section functional diagram digital section functional description the major digital subsystems within the tc835 are illustrated in figure 6, with timing relationships shown in figure 7. the multiplexed bcd output data can be displayed on lcd or led display with the tc7211a (lcd) 4-digit display driver. the digital section is best described through a discus- sion of the control signals and data outputs. run/hold input (pin 25) when left open, this pin assumes a logic "1" level. with a r/h = 1, the tc835 performs conversions continuously, with a new measurement cycle beginning every 40,002 clock pulses. when r/h changes to a logic "0," the measurement cycle in progress will be completed, and data held and displayed as long as the logic "0" condition exists. a positive pulse (>300nsec) at r/h initiates a new measurement cycle. the measurement cycle in progress when r/h initially assumed the logic "0" state must be completed before the positive pulse can be recognized as a single conversion run command. tc835 personal computer data acquisition a/d converter
3-72 telcom semiconductor, inc. personal computer data acquisition a/d converter tc835 the new measurement cycle begins with a 10,001- count auto-zero phase. at the end of this phase the busy signal goes high. strobe output (pin 26) during the measurement cycle, the strobe control line is pulsed low five times. the five low pulses occur in the center of the digit drive signals (d 1 , d 2 , d 3 , d 5 , figure 8). d 5 (msd) goes high for 201 counts when the measure- ment cycles end. in the center of the d 5 pulse, 101 clock pulses after the end of the measurement cycle, the first strobe occurs for one-half clock pulse. after the d 5 digit strobe, d 4 goes high for 200 clock pulses. the strobe goes low 100 clock pulses after d 4 goes high. this continues through the d 1 digit drive pulse. the digit drive signals will continue to permit display scanning. strobe pulses are not repeated until a new measurement is completed. the digit drive signals will not continue if the previous signal resulted in an overrange condition. the active low strobe pulses aid bcd data transfer to uarts, processors and external latches. (see application note 16.) busy output (pin 21) at the beginning of the signal-integration phase, busy goes high and remains high until the first clock pulse after the integrator zero crossing. busy returns to the logic "0" state after the measurement cycle ends in an overrange condi- tion. the internal display latches are loaded during the first clock pulse after busy, and are latched at the clock pulse end. the busy signal does not go high at the beginning of the measurement cycle, which starts with the auto-zero cycle. overrange output (pin 27) if the input signal causes the reference voltage integra- tion time to exceed 20,000 clock pulses, the overrange output is set to a logic "1." the overrange output register is set when busy goes low, and is reset at the beginning of the next reference-integration phase. underrange output (pin 28) if the output count is 9% of full scale or less ( 1800 counts), the underrange register bit is set at the end of busy. the bit is set low at the next signal-integration phase. polarity output (pin 23) a positive input is registered by a logic "1" polarity signal. the polarity bit is valid at the beginning of reference inte- grate and remains valid until determined during the next conversion. figure 8. strobe signal pulses low five times per conversion end of conversion d5 (msd) data busy b1?8 strobe d5 d4 d3 d2 d1 d4 data d3 data d2 data d1 (lsd) data d5 data note absence of strobe 201 counts 200 counts 200 counts 200 counts 200 counts 200 counts 200 counts * * delay between busy going low and first strobe pulse is dependent on analog input. tc835 outputs the polarity bit is valid even for a zero reading. signals less than the converter's lsb will have the signal polarity determined correctly. this is useful in null applications. digit drive outputs (pins 12, 17, 18, 19 and 20) digit drive signals are positive-going signals. the scan sequence is d 5 to d 1 . all positive pulses are 200 clock pulses wide, except d 5 , which is 201 clock pulses wide. all five digits are scanned continuously, unless an overrange condition occurs. in an overrange condition, all digit drives are held low from the final strobe pulse until the beginning of the next reference-integrate phase. the scanning sequence is then repeated. this provides a blink- ing visual display indication. bcd data outputs (pins 13, 14, 15 and 16) the binary coded decimal (bcd) bits b 8 , b 4 , b 2 , b 1 , are positive-true logic signals. the data bits become active simultaneously with the digit drive signals. in an overrange condition, all data bits are at a logic "0" state.
3-73 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 tc835 personal computer data acquisition a/d converter the stability of the reference voltage is a major factor in the overall absolute accuracy of the converter. for this reason, it is recommended that a high-quality reference be used where high-accuracy absolute measurements are being made. suitable references are: part type manufacturer tc04a telcom semiconductor tc9491 telcom semiconductor applications information component value selection the integrating resistor is determined by the full-scale input voltage and the output current of the buffer used to charge the integrator capacitor. both the buffer amplifier and the integrator have a class a output stage, with 100 m a of quiescent current. a 20 m a drive current gives negligible linearity errors. values of 5 m a to 40 m a give good results. the exact value of an integrating resistor for a 20 m a current is easily calculated. r int = integrating capacitor the product of integrating resistor and capacitor should be selected to give the maximum voltage swing that ensures the tolerance buildup will not saturate the integrator swing (approximately 0.3v from either supply). for 5v supplies and analog common tied to supply ground, a 3.5v to 4v full-scale integrator swing is adequate. a 0.10 m f to 0.47 m f is recommended. in general, the value of c int is given by: c int = = [10,000 clock period] i int integrator output voltage swing (10,000) (clock period) (20 m a) integrator output voltage swing a very important characteristic of the integrating capaci- tor is that it has low dielectric absorption to prevent rollover or ratiometric errors. a good test for dielectric absorption is to use the capacitor with the input tied to the reference. this ratiometric condition should read half-scale 0.9999, any deviation is probably due to dielectric absorption. polypro- pylene capacitors give undetectable errors at reasonable cost. polystyrene and polycarbonate capacitors may also be used in less critical applications. auto-zero and reference capacitors the size of the auto-zero capacitor has some influence on the noise of the system. a large capacitor reduces the noise. the reference capacitor should be large enough such that stray capacitance to ground from its nodes is negligible. the dielectric absorption of the reference capacitor and auto-zero capacitor are only important at power-on, or when the circuit is recovering from an overload. smaller or cheaper capacitors can be used if accurate readings are not required for the first few seconds of recovery. reference voltage the analog input required to generate a full-scale output is v in = 2 v ref . conversion timing line frequency rejection a signal integration period at a multiple of the 60 hz line frequency will maximize 60 hz "line noise" rejection. a 200 khz clock frequency will reject 60 hz and 400 hz noise. this corresponds to five readings per second. full-scale voltage 20 m a conversion rate vs clock frequency oscillator frequency conversion rate (khz) (conv/sec) 100 2.5 120 3 200 5 300 7.5 400 10 800 20 1200 30 oscillator frequency (khz) 60 hz 50 hz 400 hz 50.000 ? ? ? 53.333 ? 66.667 ? ? 80.000 ? 83.333 ? ? 100.000 ? ? ? 125.000 ? ? 133.333 ? 166.667 ? 200.000 ? ? 250.000 ? ? the conversion rate is easily calculated: conversion rate (readings 1/sec) = line frequency rejection clock frequency (hz) 4000
3-74 telcom semiconductor, inc. personal computer data acquisition a/d converter tc835 power supplies and grounds power supplies the tc835 is designed to work from 5v supplies. for single +5v operation, a tc7660 can provide a C 5v supply. grounding systems should use separate digital and analog ground systems to avoid loss of accuracy. displays and driver circuits telcom semiconductor manufactures two display de- coder/driver circuits to interface the tc835 to an lcd or led display. each drive has 28 outputs for driving four 7-segment digit displays. device package description tc7211aipl 40-pin epoxy 4-digit lcd driver/decoder several sources exist for lcd and led display: display manufacturer address type hewlett packard 640 page mill rd. led components palo alto, ca 94304 litronix, inc. 19000 homestead rd. led cupertino, ca 94010 and 720 palomar ave. lcd and sunnyvale, ca 94086 led epson america, inc. 3415 kanhi kawa st. lcd torrance, ca 90505 for many dedicated applications where the input signal is always of one polarity, the delay of the comparator need not be a limitation. since the nonlinearity and noise do not increase substantially with frequency, clock rates of up to ~1 mhz may be used. for a fixed clock frequency, the extra count or counts caused by comparator delay will be a constant and can be subtracted out digitally. the clock frequency may be extended above 200 khz without this error, however, by using a low-value resistor in series with the integrating capacitor. the effect of the resistor is to introduce a small pedestal voltage on to the integrator output at the beginning of the reference integrate phase. by careful selection of the ratio between this resistor and the integrating resistor (a few tens of ohms in the recommended circuit), the comparator delay can be com- pensated and the maximum clock frequency extended by approximately a factor of 3. at higher frequencies, ringing and second-order breaks will cause significant nonlinearities in the first few counts of the instrument. the minimum clock frequency is established by leakage on the auto-zero and reference capacitors. with most de- vices, measurement cycles as long as 10 seconds give no measurable leakage error. the clock used should be free from significant phase or frequency jitter. several suitable low-cost oscillators are shown in the applications section. the multiplexed output means that if the display takes significant current from the logic supply, the clock should have good psrr. zero-crossing flip-flop the flip-flop interrogates the data once every clock pulse after the transients of the previous clock pulse and half-clock pulse have died down. false zero-crossings caused by clock pulses are not recognized. of course, the flip-flop delays the true zero-crossing by up to one count in every instance, and if a correction were not made, the display would always be one count too high. therefore, the counter is disabled for one clock pulse at the beginning of the reference integrate (deintegrate) phase. this one-count delay compensates for the delay of the zero-crossing flip- flop, and allows the correct number to be latched into the display. similarly, a one-count delay at the beginning of auto-zero gives an overload display of 0000 instead of 0001. no delay occurs during signal integrate, so that true ratiometric readings result. high-speed operation the maximum conversion rate of most dual-slope a/d converters is limited by the frequency response of the comparator. the comparator in this circuit follows the inte- grator ramp with a 3 m sec delay, and at a clock frequency of 200 khz (5 m sec period), half of the first reference integrate clock period is lost in delay. this means that the meter reading will change from 0 to 1 with a 50 m v input, 1 to 2 with 150 m v, 2 to 3 at 250 m v, etc. this transition at midpoint is considered desirable by most users; however, if the clock frequency is increased appreciably above 200 khz, the instrument will flash "1" on noise peaks even when the input is shorted.
3-75 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 tc835 personal computer data acquisition a/d converter typical applications diagrams 4-1/2 digit adc with multiplexed common anode led display 20 19 18 17 12 23 7 8 16 15 14 13 11 2 1 3 9 10 22 6 5 4 6 2 1 7 5 9?5 16 bc 7777 7447 blank msd on zero d1 d2 d3 d4 d5 int out az in buff out f in +input ?nput analog common v ref in pol c ref b8 b4 b2 b1 +5v +5v x7 0.33? 200 khz + analog input 1 ? 100 k w 1 ? 4.7 k w 1 ? ?v 100 k w 100 k w 6.8 k w d b c a rbi v + c ref + tc04 tc835 r 2 r 1 f o gates are 74c04 c r 1 r 2 r 1 + r 2 1 2 c(0.41 r p + 0.7 r 1 ) 1. f o = , r p = a. if r 1 = r 2 = r 1 , f @ 0.55/rc b. if r 2 >> r 1 , f @ 0.45/r 1 c c. if r 2 << r 1 , f @ 0.72/r 1 c 2. examples: a. f = 120 khz, c = 420 pf r 1 = r 2 ? 10.9 k w b. f = 120 khz, c = 420 pf, r 2 = 50 k w r 1 = 8.93 k w c. f = 120 khz, c = 220 pf, r 2 = 5 k w r 1 = 27.3 k w rc oscillator circuit comparator clock circuits +5v v out 390 pf 30 k w 7 8 2 3 16 k w 0.22 ? 16 k w 4 1 k w 1 +5v v out 2 3 1 4 7 6 r2 100 k w r2 100 k w r3 50 k w c2 10 pf r4 2 k w c1 0.1 ? + lm311 + lm311 56 k w
3-76 telcom semiconductor, inc. personal computer data acquisition a/d converter tc835 typical applications diagrams 4-1/2 digit adc with multiplexed common cathode led display tc04 28 27 26 25 24 23 22 21 9 8 7 6 5 4 3 2 1 ref in analog gnd int out az in buff out c ref +5v ?v 6.8v ur dgnd polarity or strobe run/hold clk in busy 1 2 3 4 5 6 7 8 9 set v ref = 1v 1.22v 100 k w analog gnd 0.33 ? 100 k w 1 ? 47 k w 150 w +5v 150 w 10 11 12 13 14 15 16 17 18 +5v cd4513 be 1 ? 20 19 18 17 16 15 ?nput +input v + d5 (msd) b1 (lsb) b2 (lsd) d1 d2 d3 d4 b4 (msb) b8 10 11 12 13 14 100 k w sig in + 0.1 ? +5v f osc = 200 khz + c ref v tc835 tc04 tc7211a int out az in buff out +input ?nput analog common ref in v pol v + 20 19 18 17 16 15 14 13 12 26 27 d1 d2 d3 d4 b8 b4 b2 b1 d5 strobe or 5 31 32 33 34 30 29 28 27 v + d1 d2 d3 d4 b1 bp b3 b2 b0 gnd q r s d clk cd4071 +5v 1/4 cd4030 4-1/2 digit lcd segment drive 1 35 +5v +5v ?v + 4 5 6 10 9 3 2 1/4 cd4081 1/2 cd4030 23 cd4081 1/4 cd4030 1/2 cd4013 6.8 k w 100 k w 100 k w 100 k w 0.33 ? 1 ? analog input 1 200 khz 22 f in tc835 tc7660 11 1 +5v 8 23 (?v) v + v 24 10 ? 5 4 10 ? + + tc835 negative supply voltage generator

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